A method for performing direct current testing is employed in a semiconductor device testing apparatus wherein a large number of voltage/current generators having different voltage values are prepared for testing the direct current characteristics of the terminals (hereinafter referred to as pins) of a semiconductor device, the outputs of these numerous voltage/current generators are selectively applied to the pins of the device under test via a matrix circuit, and an arbitrary voltage is applied to each pin.
FIG. 7 shows the structure of a semiconductor device testing apparatus that uses a widely known matrix circuit. The voltage/current generator group 10 outputs various voltages V1, V2, V3, and V4; and applies these voltages V1 through V4 to the input terminals IN1 through IN4 of the matrix circuit 20. Switches S are arranged in a matrix in the matrix circuit 20, and any one of the switches S is selectively controlled to an ON state and selectively outputs one of the voltages V1 through V4 to one of the output terminals OUT1 through OUT4.
The pins P1 through P4 of the semiconductor device under test 30 are connected to the output terminals OUT1 through OUT4 of the matrix circuit 20, an arbitrary voltage among the voltages V1 through V4 is applied to each pin P1 through P4, and the direct current characteristics of the pins are measured.
In other words, a configuration is adopted whereby the presence of the matrix circuit 20 enables any voltage among the voltages V1 through V4 to be applied to any of the pins P1 through P4. A voltage source current measurement test is performed by measuring the current when each of voltages V1 through V4 is applied as to whether or not the current is within a pre-set range of values. A current source voltage measurement test is also performed, when a prescribed current is applied to the pins P1 through P4, as to whether or not a prescribed voltage is generated in the pins P1 through P4.
In the matrix circuit 20 shown in FIG. 7, when the switches S are ON state, lines connected by the switch are maintained at the same electrical potential, but when the switches are OFF state, a potential difference corresponding to the voltages V1 through V4 is presented across the switches S. Consequently, when a semiconductor switch formed from, for example, a FET (field-effect transistor), a photo-MOS relay composed of a light-emitting element and a light-receiving element, or the like is used for the switches S constituting the matrix circuit 20, a leak current occurs in the semiconductor switch at the intersecting portion in which the potential difference is presented, with the drawback of measurement error being caused by the leak current.
FIG. 8 shows the structure of a conventional semiconductor switch circuit. FIG. 8A shows a conducting state between the input terminal IN and the output terminal OUT; and FIG. 8B shows a non-conducting state between the input terminal IN and the output terminal OUT. Each of the semiconductor switches S1, S2, and S3 uses a FET, a photo-MOS relay composed of a light-emitting element and a light-receiving element, or other semiconductor switch. In the state shown in FIG. 8A in which the switches S1 and S2 are ON, and the switch S3 is OFF, the voltage VM applied to the input terminal IN is applied across the OFF semiconductor switch S3, and the leak current IR is caused to flow through the semiconductor switch S3 by application of this voltage VM.
In the state shown in FIG. 8B, in which the switches S1 and S2 are OFF, and the switch S3 is ON, a non-conducting state exists between the input terminal IN and the output terminal OUT, and the voltage applied to the input terminal IN is not fed to the output terminal. Since in this case the voltage VM applied to the input terminal IN is divided into two parts as to the semiconductor switches S1 and S2, so that leak currents IR1 and IR2 are caused to flow through the semiconductor switches S1 and S2 by these divided voltages.
The leak current IR shown in FIG. 8A and the leak currents IR1 and IR2 shown in FIG. 8B all flow through the semiconductor switch S3 or S1 and S2 by flowing out to the outside or flowing in from the outside through the input terminal IN or the output terminal OUT. Therefore, when the conventional semiconductor switch circuit shown in FIG. 8 is applied to the matrix circuit 20 shown in FIG. 7, the drawback of measurement error is caused by the leak currents flowing through the semiconductor switch circuit.
In particular, FIG. 7 shows a matrix circuit structure having four input terminals and four pins of output terminals, but a matrix circuit equipped with four or more input terminals connected to the voltage/current generator group, and a number of output terminals equal to the number of pins of the semiconductor device under test 30, is required in an actual semiconductor device testing apparatus; and the matrix circuit is large in scale. In other words, numerous switches S are used in an actual matrix circuit, and when a leak current occurs in each of such a large number of switches in an OFF state, the total quantity of leak current becomes large, and major errors result.
In the past, mechanical contact relays had to be used in order to avoid the effects of leak currents. A mercury relay has also been used due to the service life of the relay contacts in actual practice. However, since the use of mercury relays will be limited due to environmental issues, and since there is limitation on the attachment orientation of a mercury relay, the mercury relay is difficult to implement in a test head in which the matrix circuit 20 is placed near the semiconductor device under test 30, and must be mounted on the side of the testing apparatus body. Therefore, a long cable must be used to form a connection between the matrix circuit 20 and the test head.